1. Field of the Invention
This invention relates to making of power semiconductor input/output circuits and more particularly for multiple voltage applications and devices manufactured thereby.
2. Description of Related Art
U.S. Pat. No. 3,897,282 of White for a "Method of Forming Silicon Gate Device Structures with Two or More Gate Levels" describes the method for forming a gate device with two or more gate levels at Col. 1, lines 29-40, col. 2, line 63 to col. 3, line 2; FIGS. 4-7 and FIG. 9. White shows the general principle of forming a FET gate with multiple polysilicon layers separated by dielectric layers, but does not teach providing various power supply levels.
U.S. Pat. No. 5,324,676 of Guterman describes a "Method for Forming a Dual Thickness Dielectric Floating Gate Memory Cell."
U.S. Pat. No. 5,604,367 of Yang for "Compact EEPROM Memory Cell Having a Floating Gate Transistor with a Multilayer Gate Electrode" shows a method for forming a memory cell having a floating gate transistor with a multi-layer gate electrode.
U.S. Pat. No. 5,606,521 of Kuo for "Electrically Erasable and Programmable Read Only Memory with Non-Uniform Dielectric Thickness" shows forming a memory cell with non-uniform dielectric thicknesses.
U.S. Pat. No. 5,644,528 of Kojima for "Non-Volatile Memory Having a Cell Applying to Multi-Bit Data Layered Floating Gate Architecture and Programming Method for the Same" shows a method of forming a multi-bit memory cell having multiple layered floating gate.
In the past the goal of providing multiple voltage power supplies has been achieved by the steps as follows:
1. Provide multiple gate dielectrics with different thicknesses to handle various external internal power supplies. PA1 2. Regrow silicon oxides by performing a complicated process resulting in serious reliability issues.